Seminarium: Systemy Rozproszone
19 grudnia 2024 12:15, sala 4070
Michał Staniewski, Artur Kamieniecki
Memory Barriers: a Hardware View for Software Hackers
Why are memory barriers crucial in multi-core systems? This talk explores:
- Cache structure and coherence protocols,
- The role of store buffers and invalidate queues,
- Why memory barriers are a "necessary evil" for performance and scalability.
Join us to understand how modern CPUs balance speed with consistency.
Zapraszam,
Michał Staniewski
Bibliografia:
Horus: Granular In-Network Task Scheduler for Cloud Datacenters
How can datacenters manage short-lived tasks with minimal latency? This paper introduces Horus, an in-network task scheduler designed for cloud datacenters. Learn about:
- The challenges of microsecond-scale scheduling and tail response time optimization,
- Horus' architecture for datacenter-wide in-network scheduling,
- Data structures and policies for load-aware, efficient scheduling.
Zapraszam,
Artur Kamieniecki
Bibliografia: