ARMv5 instruction set.
[z ,,ARM System Developer's Guide'']
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Mnemonic   Description
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ADC        add two 32-bit values and carry
ADD        add two 32-bit values
AND        logical bitwise AND of two 32-bit values
B          branch relative +/− 32 MB
BIC        logical bit clear (AND NOT) of two 32-bit values
BKPT       breakpoint instruction
BL         relative branch with link
BLX        branch with link and exchange
BX         branch with exchange
CDP,CDP2   coprocessor data processing operation
CLZ        count leading zeros
CMN        compare negative two 32-bit values
CMP        compare two 32-bit values
EOR        logical exclusive OR of two 32-bit values
LDC,LDC2   load to coprocessor single or multiple 32-bit values
LDM        load multiple 32-bit words from memory to ARM registers
LDR        load a single value from memory
MCR,MCR2,MCRR   move to coprocessor from an ARM register or registers
MLA        multiply and accumulate 32-bit values
MOV        move a 32-bit value into a register
MRC,MRC2,MRRC   move to ARM register or registers from a coprocessor
MRS        move to ARM register from a status register (cpsr or spsr)
MSR        move to a status register (cpsr or spsr) from an ARM register
MUL        multiply two 32-bit values
MVN        move the logical NOT of 32-bit value into a register
ORR        logical bitwise OR of two 32-bit values
PLD        preload hint instruction
QADD       signed saturated 32-bit add
QDADD      signed saturated double and 32-bit add
QDSUB      signed saturated double and 32-bit subtract
QSUB       signed saturated 32-bit subtract
RSB        reverse subtract of two 32-bit values
RSC        reverse subtract with carry of two 32-bit integers
SBC        subtract with carry of two 32-bit values
SMLAxy     signed multiply accumulate instructions ((16 × 16) + 32 = 32-bit)
SMLAL      signed multiply accumulate long ((32 × 32) + 64 = 64-bit)
SMLALxy    signed multiply accumulate long ((16 × 16) + 64 = 64-bit)
SMLAWy     signed multiply accumulate instruction (((32 × 16) >> 16) + 32 = 32-bit)
SMULL      signed multiply long (32 × 32 = 64-bit)
SMULxy     signed multiply instructions (16 × 16 = 32-bit)
SMULWy     signed multiply instruction ((32 × 16) >> 16 = 32-bit)
STC,STC2   store to memory single or multiple 32-bit values from coprocessor 
STM        store multiple 32-bit registers to memory
STR        store register to memory
SUB        subtract two 32-bit values
SWI        software interrupt
SWP        swap a word/byte in memory with a register, without interruption
TEQ        test for equality of two 32-bit values
TST        test for bits in a 32-bit value
UMLAL      unsigned multiply accumulate long ((32 × 32) + 64 = 64-bit)
UMULL      unsigned multiply long (32 × 32 = 64-bit)
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Pseudoinstructions to move any 32-bit value into a register:

LDR Rd, =constant        load constant  
ADR Rd, label            load address